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RM0008
Table 9.
Sleep-now
Power control (PWR)
Sleep-now mode
Mode entry
Mode exit
Wakeup latency
Description
WFI (Wait for Interrupt) or WFE (Wait for Event) while:
– SLEEPDEEP = 0 and
– SLEEPONEXIT = 0
Refer to the Cortex?-M3 System Control register.
If WFI was used for entry:
Interrupt: Refer to Table 53: Vector table for other STM32F10xxx devices
If WFE was used for entry
Wakeup event: Refer to Section 9.2.3: Wakeup event management
None
Table 10.
Sleep-on-exit
Sleep-on-exit
Mode entry
Mode exit
Wakeup latency
Description
WFI (wait for interrupt) while:
– SLEEPDEEP = 0 and
– SLEEPONEXIT = 1
Refer to the Cortex?-M3 System Control register.
Interrupt: refer to Table 53: Vector table for other STM32F10xxx devices .
None
4.3.4
Stop mode
The Stop mode is based on the Cortex-M3 deepsleep mode combined with peripheral clock
gating. The voltage regulator can be configured either in normal or low-power mode. In Stop
mode, all clocks in the 1.8 V domain are stopped, the PLL, the HSI and the HSE RC
oscillators are disabled. SRAM and register contents are preserved.
In the Stop mode, all I/O pins keep the same state as in the Run mode.
Entering Stop mode
Refer to Table 11 for details on how to enter the Stop mode.
To further reduce power consumption in Stop mode, the internal voltage regulator can be
put in low-power mode. This is configured by the LPDS bit of the Power control register
(PWR_CR) .
If Flash memory programming is ongoing, the Stop mode entry is delayed until the memory
access is finished.
If an access to the APB domain is ongoing, The Stop mode entry is delayed until the APB
access is finished.
Doc ID 13902 Rev 9
59/995
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